The present invention relates to a cache architecture that contributes to reduced power consumption of integrated circuits. More particularly, the cache architecture permits units within the cache to be disabled on a microinstruction-by-microinstruction basis.
Issues of power consumption have become increasingly important for the design of integrated circuits. The power consumption of integrated circuits, particularly that of processors, has increased over the years with the historical increase clock speeds. Modern processors now consume so much power that the heat generated by the processors has become destructive. The increase in power consumption also contributes to reduced battery life in mobile computing applications.
Power management techniques are commonplace in the modern computer. Users of domestic personal computers recognize that computer monitors, disk drives and the like are disabled when not in use. However, such techniques are not able to keep pace with the ever increasing power demands made by newer generations of integrated circuits. Accordingly, there remains a need in the art for an integrated circuit architecture that contributes to reduced power consumption of the integrated circuit.
An internal cache may be perhaps the largest functional unit within a processor. In the Pentium Pro® processor, commercially available from Intel Corporation, an L2 cache may have a capacity to store 2 MB of data and may occupy approximately 60% of the processor's area when manufactured as an integrated circuit. If a power control technique could be applied to a processor's cache, it could achieve considerable power control savings for the chip overall.
It is known to disable (e.g. power down) a processor cache when it is not in use in order to save power. Such a technique, however, disables the cache entirely and can be used only when the cache has no operation to perform. As is known, a cache may have a high utilization rate. Accordingly, the known power conservation techniques for caches do not achieve significant reductions in power consumption.
No known power control scheme for a processor cache permits the cache to conserve power when in operation.